1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of a microwave microstrip line and/or signal line in a conventional CMOS process.
2) Description of the Prior Art
Conventional devices have the signal lines (e.g., microwave microstrip lines) near the silicon substrate. The signal lines generate e-fields near the substrate that are a problem. Due to the Si-substrate""s characteristic to dissipate energy (from the e-fields), it is difficult to fabricate a microwave microstrip line (or signal line) in the conventional CMOS process.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,504,466 (Chan-Son-Lint et al.) teaches a method that forms a microwave shifter xe2x80x9cstripxe2x80x9d.
U.S. Pat. No. 5,057,798 (Moye et al.) shows a mircostrip/ground plane on the bottom of a substrate.
U.S. Pat. No. 5,585,288 (Davis) shows a ground plane conductor.
It is an object of the present invention to provide a method for fabricating a signal line as the top metal layer.
It is an object of the present invention to provide a method for fabricating a signal line (and/or a microstrip) as the top metal layer on top of a lossless polyimide.
To accomplish the above objectives, the present invention provides a method for fabricating a signal line (and/or microstrip) as the top metal layer on top of a lossless polyimide layer which is characterized as follows.
We provide a semiconductor structure comprising a substrate having devices formed thereover and a plurality of insulating and conductive layers thereover. Next, we form ground plane over the semiconductor structure. We then form a passivation layer over the ground plane. We form a first dielectric (e.g., polyimide) layer over the passivation layer. Subsequently, we form a signal line over the first dielectric layer. The signal line is formed by a plating or printing a material selected from the group consisting of Au, Cu and Pt. We form a second dielectric layer (e.g., polyimide) over the signal line and the first dielectric layer.
In operation, the signal line generates electrical magnetic fields. These electrical magnetic fields are stopped by the first dielectric layer (e.g., polyimide) and the top metal layer (e.g., ground plane).
The invention has the following benefits: 1) can put active devices underneath the signal line which reduces chip size and 2) no backside polishing of the wafer is needed to thin the wafer.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.